The present invention relates to a semiconductor device which uses current mirror circuits to generate CMOS level signals from small amplitude signals.
With the recent trend toward higher speed and reduced power consumption in microprocessors, there has been an increasing demand for DRAMs featuring higher-speed data transfer and DRAMs permitting reduced power consumption. To meet customers' needs, efforts have been focused on the development of 288 Mbit Direct Rambus DRAM chips capable of achieving both higher-speed operations and reduced power consumption. In order to meet the customers' needs described above, it is necessary to accomplish lower internal voltages of peripheral circuits (DLL circuit and logic circuit) which are most responsible for current drain. However, the DLL circuit of the peripheral circuits is required to operate the transistors of a current mirror circuit in saturation regions to generate stable-duty clocks (duty=50±1%). For this reason, the supply voltage of the DLL circuit must be set to at least 2.0 V.
Meanwhile, the supply voltage of a logic circuit can be dropped to an extent that does not affect the characteristics of the circuit or its high-speed operation. In the development efforts, the supply voltage of the DLL circuit should be set to 2.0 V and the supply voltage of the logic circuit should be set to 1.8 V or less to satisfy the characteristics of both circuits and to realize higher-speed operation and reduced power consumption at the same time. This requires the re-designing of the level converting circuit for transferring signals between the DLL circuit and the logic circuit.
FIG. 1 is an example of a conventional level converting circuit (refer to, for example, Japanese Unexamined Patent Publication No. 11-242204).
The conventional level converting circuit performs the level conversion of small amplitude signals CLKI and CLKIB in a DLL circuit into a CMOS level signal CLKO and supplies the CMOS level signal CLKO to the logic circuit. In this case, the supply voltages of the DLL circuit and the logic circuit share the same potential.
In the conventional circuit shown in FIG. 1, if the small amplitude signal CLKI is high and the small amplitude signal CLKIB is low, then an NMOS transistor N1 is ON, while an NMOS transistor N2 is OFF, and the NMOS transistor N1 causes currents to flow from a node st1b to common. This causes the potential at the node st1b to fall from the high level to the low level, thus turning PMOS transistors P1, P3 and P6 ON.
The switching of the potential of the node st1b from the high level to the low level causes the PMOS transistor P6 to pass currents from VDDA to a node co, thereby switching the voltage level of the node co from low to high. The switching of the potential of the node co from low to high causes a node cob to be switched from high to low and the CMOS level signal CLKO from low to high.
If the small amplitude signal CLKI is low and the small amplitude signal CLKIB is high, then the NMOS transistor N1 is OFF, while the NMOS transistor N2 is ON, and the NMOS transistor N2 causes currents to flow from a node st1 to common. This causes the potential at the node st1 to fall from high to low, turning PMOS transistors P2, P4 and P5 ON.
Thus, the potential of a node coma is switched from low to high, NMOS transistors N3 and N4 are turned ON, and the potential of the node co is switched from high to low. The switching of the potential of the node co from high to low causes the node cob to be switched from low to high, and the CMOS level signal CLKO to be switched from high to low.
In the conventional circuit, the supply voltages of the DLL circuit and the logic circuit share the same potential, so that no particular attention has been paid to the potential difference in the supply voltages of the DLL circuit and the logic circuit. If, however, the power sources of the DLL circuit and the logic circuit belong to separate systems, as in this case, then changes in the potential difference between both power sources cause mismatch between the potential of the node co shown in FIG. 2 and the logic threshold of an input of the inverter, resulting in a deteriorated duty, as shown in FIG. 3. The result is illustrated in FIG. 4.
Referring to FIG. 4, when the supply voltage of the DLL circuit is set to VDDA=2.0 V, and the supply voltage of the logic circuit (VDD) is changed from 2.0 V to 1.6 V, the duty is mismatched by about 3.5%. The amount of the mismatch exceeds a design target value of 1% or less. Thus, even if the duty is adjusted in the DDL circuit, the mismatch of the duty inevitably occurs when the signal is given to the logic circuit. As a result, the adjustment is meaningless.